The present invention provides circuits for and methods of comparing values, in particular, in a microprocessor.
In one embodiment, the invention relates to circuits and methods for comparing numbers that are given as a start value and a sequence of increments, in digital circuits.
There are applications where it is to be determined at any time whether a signal reaches or passes a range of values.
Signal transitions through the range from, e.g., 10.050 to 10.060 are to be examined, whereby the values that are to be observed and are provided by e.g., a stimulating circuit are e.g., 10.000, 10.040 and 10.080 successively, given as start/increment pairs {10000, −}, {−,40}, {−, 40}. However, a simple set of two comparators (10.050≦signal≦10.060) will miss the transition through the above range as the provided signals do not have its granularity. (It is assumed here that when stimulating with the illustrated values, this implies that all (other) values from 10.050 to 10.060 are valid as well.)
The above type of comparison/determination is of interest when performing the trace of a program counter (PC) of a microprocessor. A PC circuit generates, to control the order of execution of a group of instructions, an address indicating a storage location of an arbitrary instruction code that is stored in a storage medium. Control may be performed in such a manner that instruction codes are executed in an order that is prescribed by a program. Instruction codes are designated by specifying addresses indicating their storage locations. The PC circuit generates such addresses and outputs the addresses as PC values.
The program counter is automatically incremented for each instruction cycle so that instructions are normally retrieved sequentially from the storage medium. However, certain instructions, such as branches and subroutine calls and returns, interrupt the sequence by placing a new value in the program counter.
In a superscalar CPU, trace hardware receives the absolute PC value only at special incidents, such as the beginning of trace or after a program branch, and code execution is otherwise indicated by the CPU in form of PC increments, wherein each increment indicates that one or more instructions have been executed.
A typical task of the trace hardware is to evaluate the received PC values for generation of control signals, e.g., break points. A set of comparators might be used to determine whether the CPU has executed instructions within a certain PC range, or even if it has executed only one specific instruction at a specific PC location.
Continuing with the abovementioned example and provided that the stimulating circuit is capable of providing increments from 2 to 40 in steps of 2, the trace hardware or comparing hardware has to compare all values from 10.040 to 10.080 in steps of 2 when receiving the value of 10.080 (actually the increment “{−,40}”) in a second step after receiving the value of 10.040. This plurality of comparing processes has to be performed either in the same clock cycle or sequentially, wherein, however, the following problems arise: On the one hand, doing the comparison for each calculated value entirely is costly (typically, PC values are represented with 24 to 32 or even more bits) and, on the other hand, spending extra clock cycles is highly detrimental for processor performance, in particular when the CPU provides the increments at high bandwidth.
For these or other reasons, there is a need for the present invention.